1. Field of the Invention
The present invention relates generally to flat panel displays (FPDs), and more specifically to field emission displays (FEDs). Even more specifically, the present invention relates to the cathode structure of a field emission display (FED).
2. Discussion of the Related Art
A field emission display (FED) is a low power, flat cathode ray tube type display that uses a matrix-addressed cold cathode to produce light from a screen coated with phosphor materials. FIG. 1 is a cross sectional view of a conventional FED. The FED 100 includes a cathode plate 102 and an anode plate 104, which opposes the cathode plate 102. The cathode plate 102 includes a substrate 106, cathodes or base electrodes 107 printed on the substrate 106, a first dielectric layer 108 disposed on the substrate 106 and the base electrodes 107, 109, 111, and a gate electrode 114 disposed on the first dielectric layer 108 and several emitter wells 110 formed within the gate electrode 114 and the first dielectric layer 108, such that the gate electrode 114 and the first dielectric layer 108 circumscribe each emitter well 110. A conical shaped electron emitter 112, e.g., a Spindt tip, is deposited within each emitter well 110. In order to precisely align the gate electrode 114 with the emitters 112, the wells 110 are formed by etching or cutting them out of the first dielectric layer 108 and the gate electrode 114 then depositing an emitter 112 within each well 110.
The anode plate 104 includes a transparent substrate 116 upon which is formed an anode 118. Various phosphors are formed on the anode 118 and oppose the respective emitters 112, for example, a red phosphor 120, a green phosphor 122 and a blue phosphor 124.
It is important in FEDs that the particle emitting surface of the cathode plate 102 and the opposed anode plate 104 be maintained insulated from one another at a relatively small, but uniform distance from one another throughout the full extent of the display face in order to prevent electrical breakdown between the cathode plate and the anode plate, provide a desired thinness, and to provide uniform resolution and brightness. Additionally, in order to allow free flow of electrons from the cathode plate 102 to the phosphors and to prevent chemical contamination, the cathode plate 102 and the anode plate 104 are sealed within a vacuum. In order to maintain the desired uniform separation between the cathode plate 102 and the anode plate 104 across the dimensions of the FED, structurally rigid spacers (not shown) are positioned between the cathode plate 102 and the anode plate 104.
The FED 100 operates by selectively applying a voltage potential between a respective one or more of the base electrodes 107, 109, 111 and the gate electrode 114, producing an electric field focused to cause a selective emission from the tips of the emitters 112. FIG. 2 illustrates an electric field 202 produced, which focuses on the tip of the emitter 112 in order to cause the electron emission 204. The emitted electrons are accelerated toward and illuminate respective phosphors of the anode 118 by applying a proper potential to the anode 118.
In another conventional FED illustrated in FIG. 3, an FED 300 further includes a second dielectric layer 302 disposed upon the gate electrode 114 and a focusing electrode 304 disposed upon the second dielectric layer 302. In operation, a potential is also applied to the focusing electrode 304 to collimate the electron emission from respective emitters 112. Thus, the focusing electrode 304 concentrates the electrons to better illuminate a single phosphor and to reduce the spread of electrons, this spread illustrated in the emission 204 of FIG. 2.
FIG. 4 illustrates yet another conventional FED design. In this design of the FED 400, multiple emitters 112 are deposited within wells 110 over each base electrode, e.g., base electrode 107. In operation, the electron emission from each of the emitters 112 on a given base electrode, e.g., base electrode 107, is directed toward a single phosphor, e.g., phosphor 120. Since the emission isn't focused, the phosphor 120 is slightly oversized relative to the base electrode 107 such that only the intended phosphor is illuminated.
FIG. 5 illustrates a cut-away perspective view of the conventional FED 400 of FIG. 4. As shown, the gate electrode 114 and the first dielectric layer 108 form a grid in which the generally circular-shaped emitter wells 110 are formed. In fabrication, the cathode substrate 106 is screen printed with the base electrodes 107, 109, 111 (electrode 107 is illustrated). Next, the first dielectric layer 108 is formed over the substrate 106 and the respective base electrodes 107, 109, 111. A gate electrode layer is applied over the first dielectric layer 108. The wells 110 and gate electrode 114 are formed by etching the first dielectric layer 108 and the gate electrode layer. Then, an emitter 112 is deposited into each well 110.